There is increasing demand for use of a high frequency signal detector or RF signal detector as a trigger signal output circuit in radio communication devices of an RFID (Radio Frequency Identification) system and DSRC (Dedicated Short-Range Communication) system, etc.
When an RF signal detector circuit is used as a trigger signal output circuit, some qualities that are sought are low power consumption, low operating voltage and a high signal detection sensitivity, etc.
A configuration of the kind shown in FIG. 7 has been described in Patent Document 1 (Japanese Patent Kokai Publication No. JP-P2006-174101A) in order to satisfy this requirement. It should be noted that FIG. 7 is a configuration created based upon the content of FIGS. 1 and 3 of Patent Document 1. The configuration and operation of FIG. 7 will be described based upon the content set forth in Patent Document 1.
As shown in FIG. 7, P-channel transistors Tr13 and Tr23 having their sources coupled together, a P-channel transistor Tr31 forming a current source and N-channel transistors Tr15 and Tr25 forming a passive load (current mirror circuit) constitute a differential amplifying circuit. A first series circuit composed of diode-connected NPN bipolar transistors Tr11 and Tr12 (detector diodes) and a capacitor C11 is disposed between a power supply Vcc and ground, and an NPN bipolar transistor (current source) Tr14 is connected between the cathode of the detector diode Tr12 and ground. Further, a second series circuit composed of diode-connected NPN bipolar transistors Tr21 and Tr22 (detector diodes) and a capacitor C21 is disposed between the power supply Vcc and ground, and an NPN bipolar transistor (current source) Tr24 is connected between a cathode of the detector diode Tr22 and ground. A matching circuit 10 including a series capacitor is connected to the anode of the detector diode Tr12.
Furthermore, a bipolar transistor Tr34 having an emitter grounded and a collector and base that are connected to a current source, and bipolar transistors Tr33, Tr14 and Tr24 having emitters grounded and bases coupled together and connected to the base of the transistor Tr34, constitute a current mirror. A transistor Tr32, which has a source connected to the power supply and a drain and collector that are connected to the collector of the bipolar transistor Tr33, and a current-source transistor Tr31 constitute a current mirror.
A high-frequency signal (RF signal) received from an antenna 11 is applied to the anode of the detector diode Tr12 via the matching circuit 10 and charges the capacitor C11 upon being rectified by the detector diode Tr12. The voltage across the terminals of the capacitor C11 takes on a value that conforms to the amplitude (envelope) of the high-frequency signal. Since the high-frequency signal does not flow into the second series circuit (transistors Tr21, Tr22 and capacitor C21), the voltage across the terminals of the capacitor C21 does not rise. The difference voltage between the terminal voltages of the capacitors C11 and C21 is amplified by the differential amplifying circuit, which delivers a differential output signal Vout1 to an amplifier 200, which is the next stage. The capacitor C10 in the matching circuit 10, the diode Tr11, the detector diode Tr12 and the capacitor C11 constitute a voltage doubling circuit and, hence, the terminal voltage of the capacitor C11 takes on a voltage that is double the amplitude of the high-frequency signal. As a result, the difference between the two inputs to the differential amplifying circuit is doubled and sensitivity is improved.
It should be noted that Patent Document 2 discloses an operational transconductance amplifier (OTA) capable of operating at high speed for improving the noise characteristic, the amplifier comprising an input differential pair, a constant current source (cascode-connected transistors), a bias circuit, a common-mode feedback (CMFB) circuit and a conductance control circuit. In Patent Document 2, the CMFB circuit generates a reference current in order that the mid-point voltage of differential voltages corresponding to the differential output currents of the input differential pair will be the same voltage as a reference voltage, and a constant current circuit connected to the output pair of the differential pair and constructed by the cascode-connected transistors supplies the differential pair with a differential current mirror current that is in accordance with the reference current generated by the CMFB circuit.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2006-174101A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2003-243947A
The entire disclosures of Patent Documents 1 and 2 are incorporated herein by reference thereto. The following analyses are given by the present inventor.
The inventor has studied the circuit configuration illustrated in FIG. 7, and the results of these studies will now be described.
As mentioned above, the signal received by the antenna 11 is applied to the detector circuit 100, in which amplitude information is detected by the diode detector circuit (transistors Tr11, Tr12, capacitor C11, transistors Tr21, Tr22 and capacitor C21) and the signal is amplified by the differential amplifying circuit (differential-input/single-ended output amplifying circuit). The resultant signal is supplied to the amplifier 200 constituting the next stage.
The output section of the detector circuit 100 outputs the differential signal Vout1 irrespective of the fact that it is a differential-input/single-ended output amplifying circuit. That is, the output section includes a diode detector circuit of half-wave voltage doubling type (NPN diodes in two stages) and constant current sources (transistors Tr14, Tr24), and the detector output section has the capacitors (C11, C21) for smoothing voltage. The diode detector circuit performs envelope detection, i.e., demodulates the amplitude-modulated signal and detects an AM-type burst (intermittent) signal component with regard to a certain frequency carrier. The next stage has a differential-input/single-ended output amplifier of the PNP input so as to make low-voltage drive possible. This amplifier amplifies the detection signal.
The amplifier in the output section of the detector circuit 100 is the amplifier of a single-ended output and produces the quasi differential output Vout1 artificially. This differential output Vout1 is supplied to the amplifier 200, which further amplifies the detection signal to thereby finally obtain a detection signal output Vout2.
However, the output signal Vout1 is not a pure differential signal; in view of the circuit configuration and principle of operation, the signal is substantially a single-ended signal. Although it may appear at a glance that the circuit outputs a differential signal, this is not the case.
With such a circuit configuration and principle of operation, the common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are decided by the capability of the amplifier in the initial stage. Consequently, the CMRR and PSRR of the entire detector circuit 100 deteriorate. If it is attempted to raise the gain of the entire detector circuit 100 in order to improve signal detection sensitivity, the fact that the CMRR and PSRR are poor results in unstable operation of the detector circuit, such as abnormal oscillation and a decline in the SNR (signal-to-noise ratio) of the output signal, and a high detection sensitivity cannot be achieved.
On the other hand, in a case where the detection signal that has been output from the amplifier is binarized, a problem which arises is that depending upon the status of the SNR of the amplifier output, this can lead to malfunction unless the threshold value of the binarization circuit is adjusted skillfully.
Thus, although it appears at a glance that the output section Vout1 of the detector circuit 100 outputs a differential signal, the amplifier section of the detector circuit 100 is a single-ended signal output circuit and does not operate as one that outputs a differential signal.
Since the output of the amplifier section of the detector circuit 100 is not a fully differential output signal, the CMRR and PSRR are poor and it is difficult to achieve stable operation when a high gain is set. This point will be described later in comparison with the present invention.